Non-volatile semiconductor memory devices include a single poly EEPROM having a single polysilicon layer functioning as a gate, a stack gate, such as an ETOX, having two vertically stacked polysilicon layers, and a dual poly and a split gate corresponding to intermediates between the single poly EEPROM and the split gate.
Generally, the stack gate-type memory device has the smallest cell size but has a complicated circuit, and thus, is suited for high-density or high-performance applications. On the other hand, the stack gate-type memory device is not suited for low-density applications. The EEPROM is mainly used for low-density applications. For example, the single poly EEPROM is fabricated by adding two mask processes to a logic process.
FIG. 1 is a plan view illustrating a single poly EEPROM cell while FIG. 2 is a longitudinal-sectional view taken along the line Y-Y′ of the EEPROM cell of FIG. 1.
As illustrated in FIG. 1, a single poly EEPROM cell performs a programming operation and an erasing operation using an FN (Fowler-Nordheim) tunneling method. The single poly EEPROM cell is divided into tunneling region 50 having well 10A and active region 20A, read transistor region 52 having active region 20B and well 30, and control gate region 54 having well 10B and active region 20C. Polysilicon pattern 40 is formed on and/or over tunneling region 50, read transistor region 52 and control gate region 54. If an N-MOS structure is used, well 10A of the tunneling region 50 and well 10B of the control gate region 54 are an N-type, while well 30 of read transistor region 52 is a P-type. In this case, it is necessary to isolate a P-type semiconductor substrate and the EEPROM cell from each other.
Tunneling of electrons in tunneling region 50 is generated using a coupling ratio between capacitance A of tunneling region 50 and capacitance B of control gate region 54, thereby performing programming/erasing operations. In the programming/erasing operations, in order to properly increase the coupling ratio between capacitance A of tunneling region 50 and capacitance B of control gate region 54, the dimensions of control gate region 54 are increased, thereby increasing the dimensions of an area where active region 20C of control gate region 54 and polysilicon pattern 40 overlap with each other. Thereby, the overall size of the cell is increased.
Accordingly, in an EEPROM of several tens of bits or more, the overall size of an EEPROM cell is increased, and thus cell density is lowered. Moreover, in case that a dual poly EEPROM cell is fabricated in order to enhance cell density, a process of forming a separate insulating film for capacitance of a control gate region or a process of manufacturing a separate control gate is required, thereby complicating the fabrication of the dual poly EEPROM cell.